The present invention relates, in general, to the field of adaptive or reconfigurable processors. More particularly, the present invention relates to a multi-adaptive processor (“MAP™”, a trademark of SRC Computers, Inc., assignee of the present invention) element architecture incorporating both course and fine grained reconfigurable elements.
Adaptive processors, sometimes referred to as reconfigurable processors, are processor elements that have the ability to alter their hardware functionality based on the program they are running. When compared to a standard microprocessor that can only sequentially execute pre-implemented logic, the adaptive processor has the ability to perform thousands of times more efficiently on a given program. When the next program is run, the logic is reconfigured via software, to again perform very efficiently. The integrated circuits used in these adaptive processors have historically fallen into two categories, namely the custom coprocessor application specific integrated circuits (“ASICs”), and the field programmable gate arrays (“FPGAs”).
Many architectures have been proposed for custom integrated circuit chips containing both microprocessor features and programmable logic portions. These chips however, represent a poor implementation for high performance general purpose adaptive computing since they still have the very high non-recurring costs associated with a high performance custom ASIC, which in turn requires very large markets to make them economically viable. In addition, since both the normal microprocessor and the programmable logic are formed on the same die, the amount of reconfigurable logic will necessarily be much less than if they were each in provided as a discrete part. Since the performance of an adaptive processor is directly proportional to the number of gates it can utilize, this solution is severely limited and is best suited for specialized, limited use, adaptive processors.
An alternative to this approach is to use FPGAs to accomplish the adaptive computing function. However, these chips have historically been relatively small in terms of gate count. In addition, some portion of the gates of the FPGA also had to be used for control functions needed to communicate with the rest of the system. This led to their use primarily in board level products that were designed to target specific families of applications with limited input/output (“I/O”) functionality. However, with recent advances in FPGA geometry, features and packaging, it has now become possible to implement new board level architectures that can be used to accomplish large scale high performance general purpose adaptive computing. One such computer is based on the unique SRC Computers, Inc. MAP™ multi-adaptive processor element architecture disclosed herein.
In the past, reconfigurable processors have been constructed using a variety of components containing fine grained logic elements such as those which are found in FPGAs. Fine grained logic elements are circuit elements that each perform very low level functions such as an AND or OR gate, or slightly larger functions such as counters. SRC Computers' MAP processor is one example of this type of reconfigurable processor. These fine grained devices allow for very versatile and relatively easy implementations of any desired function.
Nevertheless, as computer software such as SRC Computers' Carte™ programming environment has become available allowing more effective utilization of this form of processor, certain shortcomings of implementing reconfigurable processors in this fashion have become apparent. That is, while virtually any function can be implemented with fine grain logic elements, it may require a very large number of these elements to create very complex functions such as, for example, a 64 bit multiplier for floating point format numbers. As a result, only small quantities of such complex functional units can be implemented in a reconfigurable processor even if the largest FPGAs are used. Further, since reconfigurable processors generally exhibit relatively low clock rates compared to those of microprocessors, (and rely upon the parallelism of many functional units to exceed the performance of standard microprocessors), the relatively low number of functional units can result in rather poor performance.
One of the methods used by SRC Computers to limit the impact of this is to utilize two identical FPGAs back-to-back on the MAP processor as disclosed in U.S. patent application Ser. No. 10/142,045. This technique enables a doubling of the number of logic elements resulting in a theoretical doubling in performance and can be accomplished based upon certain unique characteristics of FPGA packages and the use of two functionally identical FPGAs. An alternative technique would be to replace the reconfigurable FPGAs with some higher density device such as an ASIC. However, this would result in unacceptably limited functionality since ASICs are not reconfigurable devices and would only perform the specific function for which they were designed.